Academic Webpage

Experience

>> On-chip RX/TX matching network for a single antenna

>> High Frequency Analog Buffer Design

>> High-Efficiency RF Power Amplifier

>> CMOS Rectifier for RF Energy-Harvesting

>> Transformer Design and EM simulations

>> PCB Design for IC Testing

>> Low Noise Amplifier (LNA) Design for Ultra-Low-Power BLE Transceiver

> Designed, laid out, simulated and taped out a Low-Power LNA in 65nm TSMC

> Used Rg effect for Input Matching to Antenna

> Measured S-Parameters (S11, S21, S21), Noise, IIP1 and IIP3

>> Low-Power Mixer (Mixer) and Common Mode Feedback (CMFB) differential amplifier

> Designed, laid out, simulated and taped out a Low-Power LNA in 65nm TSMC

> Used differential type mixer.

> Measured S-Parameters (S11, S21, S21), Noise, IIP1 and IIP3

>> Tuning Amplifier Design

>Designed Tuning Amplifier to adjust load of AlN Resonator.

> Used center-tapped Inductor to have differential output.

>>Wideband Programmable Gain Amplifier (PGA) for the Front-End of a Phased Array Receive

>Designed a PGA, which is differential and digitally programmable with 4-bit control (IBM 45nm SOI technology).

>Employed a differential amplifier topology based on flipped voltage follower (FVF) cell.

>Achieved wide band with FVF cell by having additional zero without extra power consumption.

>>Low Noise Amplifier (LNA) Design for the Front-End of a Phased-Array Receiver

>Designed a fixed-gain single-ended input to differential output LNA for a 5G millimeter-wave communication link in IBM 45nm SOI (Silicon on Insulator) technology.

>Designed a transformer to convert single-ended input to differential output.

>Employed ADS Momentum E&M simulator to simulate transformer and other passive components used in design. Thereby, including substrate effects on passive component.

>>Comparator Design

>Designed a comparator Circuit for a flash Analog Digital Converter (ADC) in a high-speed serial link in 45nm CMOS technology. Main specifications: Clock rate, kickback noise, probability failure, offset voltage, Hysteresis, input and output capacitors.

>Chose a double tail Latch-type topology: topology achieves fast decision due to its strong positive feedback.

>Achieved sensing differential input and performing comparison by speedy latch type circuit.

>>Operational Amplifier (OPAMP) Design

>Designed an Operational Amplifier circuit in 45nm CMOS Technology using Cadence (Spectre Simulator and Virtuoso).

>Completed specifications: Open and closed loop gains, stability, slew rate, output swing, pass-band flatness, input common-mode and offset voltages.

>Performed Monte Carlo Simulations to adjust the effect of process, mismatch, and environment variations on design.

>Laid out, Cleared Design Rules Check (DRC) and Layout vs Schematic (LVS).

>> Wideband Transimpedance Amplifier (TIA) Design

>Designed a Transimpedance Amplifier in 45nm CMOS Technology using CAD system Cadence Virtuoso.

>Simulated with Cadence Spectre circuit simulator in Analog Design Environment (ADE) tool to assess performance with model files.

>Performed Monte Carlo Simulations to evaluate yield of performance under circumstances of process variations and device mismatch (Yield for impedance, bandwidth, peaking and output peak to peak voltage).